Electroxcape

Welcome to the ELECTROXCAPE - by M S Ramaiah University of Applied Sciences!

About the Opportunity:

Teams of four progress through three common engineering missions followed by a semi-final and final.

• Round 1 — a timed system-intelligence challenge involving waveforms, protocols, RTL and circuit evidence.
• Round 2.1 — hands-on fault forensics using deliberately faulty hardware.
• Round 2.2 — implement a constrained system and adapt when a requirement changes.
• Semi-final — the top eight teams face a Blind Handoff, where one pair designs a solution and another implements it using only the provided documentation.
• Final — the top four compete in a final challenge.

Timeline:

All timings below are shown as elapsed time from the start of the event, T+0:00, running to the mandatory three-hour ceiling at T+3:00. Registration and team seating must be completed before T+0:00. No lunch or unstructured break is built into the schedule — every minute from T+0:00 to T+3:00 is allocated to briefing, an active round, or the judging/announcement window needed to run the next round.

• 0:00–0:10 (10 min) — Briefing, safety rules, team verification and mission briefing.
• 0:10–0:50 (40 min) — ROUND 1: SIGNAL INTELLIGENCE. All teams solve an integrated evidence board containing waveform/protocol identification, component evidence, Boolean/RTL reasoning and a final unlock condition. Automatic/answer-sheet verification is used wherever possible.
• 0:50–1:00 (10 min) — Judging window. Round 1 sheets are scored and the cohort advancing to Round 2 is announced.
• 1:00–1:45 (45 min) — ROUND 2A: FAULT FORENSICS. All teams receive identical faulty circuit boards/breadboard systems containing multiple seeded faults. Teams diagnose using visual inspection and DMM measurements, submit root cause and corrective action, then demonstrate the repair. Two judges can sample demonstrations while standardised fault sheets control scoring.
• 1:45–2:15 (30 min) — ROUND 2B: SYSTEM RECONFIGURATION. All teams receive a constrained system requirement and a fixed component inventory. They must derive the logic, wire the system and produce the required output. At the halfway point, a controlled specification change is announced; teams must adapt the existing design.
• 2:15–2:25 (10 min) — Judging window. Round 2A/2B scores are combined and the top eight teams advancing to the Final are announced.
• 2:25–3:00 (35 min) — FINAL: BLIND HANDOFF. Each of the top eight teams is split into a Design Pair and a Build Pair. The Design Pair receives a system requirement and produces a complete implementation sheet. The document is sealed and handed to the Build Pair, who must implement it without verbal clarification. Judges evaluate correctness, documentation and implementation fidelity.

Operational principle: the event uses identical kits, fixed stations, standardised answer sheets and short judging windows to prevent queues and keep the event within the three-hour, T+0:00–T+3:00 window.

Rules:

• Each team consists of exactly four registered participants.
• Only organiser-provided components, instruments and reference sheets may be used.
• Phones, internet searches, AI tools and external assistance are prohibited during active rounds.
• Teams must remain at their assigned station unless movement is explicitly permitted.
• Every member must participate; judges may direct questions to any member.
• Teams may request clarification of wording, but judges will not provide technical solutions.
• Deliberate damage, tampering with another team's setup or copying results may lead to disqualification.
• When time is called, all work must stop immediately.
• Elimination is based on the published round score; scores do not carry forward after a cut.
• The organisers may issue controlled system updates or fault injections stated in the round instructions.

Eligibility: ECE and related engineering students.