Wire2Win Amalthea'26

Overview

Wire2Win is Amalthea's premier hands-on electrical engineering and hardware synthesis competition hosted at IIT Gandhinagar. Moving away from purely theoretical calculations or isolated breadboarding exercises, Wire2Win challenges student engineers to design, build, and debug a multi-stage, synchronized digital hardware system from raw logic gates and discrete active/passive components under strict time constraints.

In this intense 3-hour hardware sprint, teams must fabricate a 2-Bit Synchronous Accumulator with Latching Overflow and Debounced Bus Control on solderless breadboards, bridging combinational logic engine design with sequential state registers and real-time fault protection units.

Subsystem Architecture & Technical Problem

Teams will engineer a self-contained digital machine comprising four interdependent subsystems:

• Mechanical Debouncer & Manual Clock Unit (SR Latch): Eliminate mechanical switch bounce chatter using an SR cross-coupled NAND/NOR latch to generate clean, single-pulse clock (CLK) transitions.
• 2-Bit Binary Adder Engine (Combinational Processing): Construct a full arithmetic adder utilizing discrete TTL 74-series logic gates to perform binary addition of external 2-bit input operands to current stored feedback states.
• Synchronous State Register (Dual D Flip-Flops): Drive positive-edge-triggered dual D Flip-Flops (IC 7474) with debounced clock pulses to retain accumulator output states and feed status LEDs.
• Asynchronous Overflow Supervisory Unit (SR Fault Latch): Monitor arithmetic carry-out (Cout) to set a persistent Red "OVERFLOW" latch that remains ON across subsequent clock cycles until manually cleared by a reset switch.

Eligibility & Team Rules

• Eligibility: Open to all undergraduate students enrolled in any recognized engineering college or university.
• Target Audience: First- and second-year undergraduate engineering students across all disciplines (especially electrical, electronics, and digital logic backgrounds).
• Team Size: Teams of 2 to 3 members. (Solo participation is strictly disallowed to foster real-time bench debugging and collaboration).
• Composition: Cross-departmental, cross-batch, and cross-college teams are fully permitted.

Provided Hardware & Test Bench

Each team workstation will be supplied with an identical hardware kit:

• Bench Equipment: Regulated Dual DC Bench Power Supply (5V fixed), Digital Storage Oscilloscope (DSO, min. 20MHz), Digital Multimeter (DMM), and 2x Solderless Breadboards (830 tie-points each).
• Digital IC Pool (74-Series TTL): 7400 (Quad NAND), 7402 (Quad NOR), 7408 (Quad AND), 7432 (Quad OR), 7486 (Quad XOR), and 7474 (Dual D Flip-Flop).
• Passives & Hardware: Status LEDs (Green, Yellow, Red, Blue), current-limiting resistors, pull-up/pull-down resistors, SPDT slide switches/pushbuttons, and solid-core jumper wires.

Rules & Disqualification Guidelines

• Zero External Simulators/Tools: Use of smartphones, laptops, online simulators (Tinkercad, Falstad, Proteus), or external communication will lead to immediate disqualification.
• Pre-Assembled Modules: Using pre-wired jumpers, pre-soldered sub-modules, or non-issued ICs is strictly prohibited.
• Supply Short-Circuit Penalties: Power rail shorts that trip bench supply limits incur a -5 Point penalty per event.
• Damaged ICs: One free IC replacement is permitted for pin breakage. Additional chip damage due to reverse polarity (Vcc to GND) incurs a -5 Point penalty per chip.
• Lab Safety: Operating live circuits without power isolation during modifications will forfeit certification.

Evaluation & Scoring Criteria (100 Points Total)

• Combinational Arithmetic Accuracy (20 Points): Error-free 2-bit binary addition across all input permutations (00, 01, 10, 11).
• Clock Debounce & Edge Integrity (15 Points): Bounce-free manual clock triggering verified on DSO.
• Sequential Storage & State Feedback (20 Points): Positive-edge state transitions on D Flip-Flops with continuous state accumulation over 5+ cycles.
• Supervisory Latch & Fault Retention (20 Points): Reliable capture of arithmetic overflow (Cout=1), persistent Red LED latching, and clean manual fault resets.
• Breadboard Ergonomics & Rail Hygiene (10 Points): Low-profile wiring, color-coded power/ground lines, absence of "bird's nests," and proper LED current limiting.
• Technical Defense & Viva-Voce (15 Points): Team's ability to explain propagation delays, setup/hold times, IC pin functions, and troubleshooting steps.

Rewards & Perks

• Cash Prizes & Trophies: Awarded to top-scoring teams based on bench evaluation and demonstration timestamp.
• Certificates: Certificates of Excellence for winners/finalists and Certificates of Participation for all qualifying teams.