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ASIC Engineer Internship - Design

MetaBangalore
Internship
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Deadline: 12/11/2026
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About the role

Meta is hiring for the role of ASIC Engineer Intern, Design!

Responsibilities of the Candidate:

- Participate in Micro-architecture, Design, and Verification reviews and provide feedback - Design and develop RTL or HLS code for some of the IPs - Analyze designs and enhance PPA (Power, Performance, Area) - Support and develop Verification Infrastructure, analyze and improve Verification Coverage - Support Simulation accelerators and post-Silicon validation

Knowledge of Verilog or System Verilog or HLS

- Knowledge of Computer Architecture and Logic Design fundamentals - Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment - Intent to return to degree-program after the completion of the internship/co-op - Currently has, or is in the process of obtaining, a Masters or PhD degree in Electrical Engineering, Computer Engineering or related engineering fields - Experience with Lint, Synthesis, Formal or Physical Design tools - Scripting experience with Python or Perl -

Experience with High Performance Computing

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Experience with Digital Signal Processing Techniques

- Creativity and problem solving

Requirements

- Currently has, or is in the process of obtaining, a Bachelor's degree in Electrical Engineering, Computer Engineering or related engineering fields -

Skills for this role

Skills we detected for this role.

  • Python
  • Verilog / VHDL