Responsibilities of the candidate:

Develop and refine physical chip designs, including cell and block-level semi-custom layouts, FUB-level floor plans, abstract view generation, and schematic-to-layout verification.
Conduct reliability verification, debug issues, and apply proactive intervention strategies to optimize chip performance.
Utilize parasitic extraction, custom polygon editing, auto-place and route algorithms, floor planning, and full-chip assembly techniques to ensure design success.
Collaborate across teams to troubleshoot complex design challenges and deliver high-quality solutions.
Participate in the execution of project methodologies, flow developments, and verification processes.

Requirements:

Bachelor's degree in Electronics, Electrical Engineering, or a related field with 0-1 years of hands-on experience in physical design, including skills gained through internships, academic projects, coursework, or hands-on training OR a Master's degree in Electronics, Electrical Engineering, or a related field with no prior professional experience.
Basic understanding of layout design and verification processes. - Familiarity with ICC2 tools. - Proficiency in TCL scripting is a plus.

Strong problem-solving skills and ability to troubleshoot complex design challenges effectively.
Excellent collaboration and communication skills to work across diverse teams.
Demonstrated interest in advancing semiconductor technologies and methodologies.