About the role
Design Verification Engineer Intern (Toronto)
Location: Toronto, Ontario, Canada
Employment type: Internship
About Astera Labs
Astera Labs develops purpose-built connectivity solutions for rack-scale AI infrastructure. Our Intelligent Connectivity Platform brings together high-performance connectivity technologies for AI, cloud, server, and networking systems.
The role
As a Design Verification Engineer Intern in Toronto, you will help verify complex digital designs for connectivity products. You will contribute to simulation-based verification, create and run tests, analyze waveforms and logs, and help improve functional coverage and reusable verification infrastructure.
This internship is an opportunity to build hands-on experience at the intersection of digital design, computer architecture, verification methodology, and software tooling while taking ownership of meaningful verification work.
What you'll do
- Develop, modify, and run simulation-based tests for digital design and connectivity IP blocks. - Contribute to SystemVerilog and UVM-based verification environments, including tests, sequences, agents, scoreboards, monitors, and checkers. - Run individual tests and regressions, review build and simulation results, and triage failures. - Debug functional issues by analyzing logs, transactions, register activity, and waveform databases with industry-standard tools. - Add or update test definitions, regression lists, manifests, and scripts as verification requirements evolve. - Track functional and code-coverage results and help identify meaningful coverage gaps. - Work with reusable verification infrastructure, protocol agents, reset and interrupt components, register models, and scoreboards. - Explore assertions, formal verification, or emulation workflows when appropriate for the design and project. - Collaborate with design, architecture, emulation, and verification engineers to reproduce issues and communicate findings. - Document test intent, debug conclusions, verification procedures, and project progress.
What you bring
Basic qualifications
- Currently pursuing a bachelor's or master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. - Coursework, project, research, or hands-on experience with digital logic, computer architecture, RTL, or hardware verification. - Programming or scripting experience in SystemVerilog, Verilog, C/C++, Python, or a comparable language. - Familiarity with Linux development environments, command-line tools, and Git or another source-control system. - Strong analytical and debugging skills, with an interest in understanding complex hardware behavior. - Strong written and verbal communication, organization, and time-management skills. - A hands-on work ethic, curiosity, learning agility, and ability to take ownership of assigned deliverables.
Requirements
Preferred qualifications
- Experience with SystemVerilog, UVM, constrained-random verification, assertions, or functional coverage. - Familiarity with simulation, waveform-debug, regression, or coverage tools such as VCS, Verdi, DVE, or equivalent tools. - Experience writing testbenches, sequences, scoreboards, monitors, checkers, or reference models. - Exposure to AXI, APB, PCIe®, CXL®, memory systems, fabrics, controllers, or other high-speed digital interfaces. - Familiarity with formal verification, emulation, RTL simulation, or register-abstraction-layer models. - Experience using Python, Tcl, or shell scripting to automate verification workflows and analyze results.